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8624byi www.idt.com rev. c july 30, 2010 1 ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer g eneral d escription the ics8624i is a high performance, 1-to-5 differential-to-hstl zero delay buffer. the ics8624i has two selectable clock input pairs. the clk0, nclk0 and clk1, nclk1 pair can accept most standard differential input levels. the vco operates at a frequency range of 250mhz to 630mhz. utilizing one of the outputs as feedback to the pll, output frequencies up to 630mhz can be regenerated with zero delay with respect to the input. dual reference clock inputs support reduntant clock or multiple reference applications.. b lock d iagram p in a ssignment f eatures ? fully integrated pll ? five differential hstl compatible outputs ? selectable differential clkx, nclkx input pairs ? clkx, nclkx pairs can accept the following differential input levels: lvpecl, lvds, hstl, sstl, hcsl ? output frequency range: 31.25mhz to 630mhz ? input frequency range: 31.25mhz to 630mhz ? vco range: 250mhz to 630mhz ? external feedback for ?zero delay? clock regeneration ? cycle-to-cycle jitter: 35ps (maximum) ? output skew: 50ps (maximum) ? static phase offset: 30ps 125ps ? 3.3v core, 1.8v output operating supply ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v ddo q3 nq3 q2 nq2 q1 nq1 v ddo sel0 sel1 clk0 nclk0 clk1 nclk1 clk_sel mr v ddo q0 nq0 gnd gnd fb_in nfb_in v dd v ddo nq4 q4 gnd gnd v dda pll_sel v dd 32-lead lqfp 7mm x 7mm x 1.4mm body package y package top view ics8624i pll_sel clk0 nclk0 clk1 nclk1 clk_sel fb_in nfb_in sel0 sel1 mr q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 0 1 pll 0 1 4, 8
ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer 8624byi www.idt.com rev. c july 30, 2010 2 t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 10 l e st u p n in w o d l l u p . 3 e l b a t n i d e t o n e g n a r y c n e u q e r f t u p t u o d n a t u p n i e h t s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 21 l e st u p n in w o d l l u p . 3 e l b a t n i d e t o n e g n a r y c n e u q e r f t u p t u o d n a t u p n i e h t s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 30 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 40 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 51 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 61 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 7l e s _ k l ct u p n in w o d l l u p s t c e l e s , h g i h n e h w . 0 k l c n , 0 k l c s t c e l e s , w o l n e h w . t u p n i t c e l e s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p n i 1 k l c n , 1 k l c 8r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a x q n s t u p t u o d e t r e v n i e h t d n a w o l o g o t x q s t u p t u o e u r t e h t g n i s u a c t e s e r e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e 2 3 , 9v d d r e w o p. s n i p y l p p u s e r o c 0 1n i _ b f nt u p n ip u l l u p . " y a l e d o r e z " h t i w s k c o l c g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f 1 1n i _ b ft u p n in w o d l l u p . " y a l e d o r e z " h t i w s k c o l c g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f 3 1 , 2 1 9 2 , 8 2 d n gr e w o p. d n u o r g y l p p u s r e w o p 5 1 , 4 10 q , 0 q nt u p t u o 0 5 . s t u p t u o k c o l c l a i t n e r e f f i d . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t s h , 7 1 , 6 1 5 2 , 4 2 v o d d r e w o p. s n i p y l p p u s t u p t u o 9 1 , 8 11 q , 1 q nt u p t u o 0 5 . s t u p t u o k c o l c l a i t n e r e f f i d . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t s h 1 2 , 0 22 q , 2 q nt u p t u o 0 5 . s t u p t u o k c o l c l a i t n e r e f f i d . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t s h 3 2 , 2 23 q , 3 q nt u p t u o 0 5 . s t u p t u o k c o l c l a i t n e r e f f i d . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t s h 7 2 , 6 24 q , 4 q nt u p t u o 0 5 . s t u p t u o k c o l c l a i t n e r e f f i d . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t s h 0 3v a d d r e w o p. n i p y l p p u s g o l a n a 1 3l e s _ l l pt u p n ip u l l u p . s r e d i v i d e h t o t t u p n i e h t s a k c o l c d n a l l p e h t n e e w t e b s t c e l e s . k c o l c e c n e r e f e r s t c e l e s , w o l n e h w . l l p s t c e l e s , h g i h n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l : 1 e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
8624byi www.idt.com rev. c july 30, 2010 3 ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer t able 2. p in c haracteristics t able 3a. c ontrol i nput f unction t able t able 3b. pll b ypass f unction t able s t u p n i s t u p t u o 1 = l e s _ l l p e d o m e l b a n e l l p 1 l e s0 l e s* ) z h m ( e g n a r y c n e u q e r f e c n e r e f e r4 q n : 0 q n , 4 q : 0 q 00 0 3 6 - 0 5 21 01 5 1 3 - 5 2 11 10 5 . 7 5 1 - 5 . 2 61 11 5 7 . 8 7 - 5 2 . 1 31 . z h m 0 0 7 o t z h m 0 5 2 s i e v o b a s n o i t a r u g i f n o c l l a r o f e g n a r y c n e u q e r f o c v : e t o n * s t u p n i s t u p t u o 0 = l e s _ l l p e d o m s s a p y b l l p 1 l e s0 l e s4 q n : 0 q n , 4 q : 0 q 00 4 01 4 10 4 11 8 l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer 8624byi www.idt.com rev. c july 30, 2010 4 t able 4a. p ower s upply dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 6 . 18 . 10 . 2v i d d t n e r r u c y l p p u s r e w o p 0 2 1a m i a d d t n e r r u c y l p p u s g o l a n a 5 1a m i o d d t n e r r u c y l p p u s t u p t u od a o l o n0a m t able 4b. lvcmos / lvttl dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i , 1 l e s , 0 l e s r m , l e s _ k l c v d d v = n i v 5 6 4 . 3 =0 5 1a l e s _ l l pv d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i , 1 l e s , 0 l e s r m , l e s _ k l c v d d v , v 5 6 4 . 3 = n i v 0 =5 -a l e s _ l l pv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a t able 4c. d ifferential dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i n i _ b f , 1 k l c , 0 k l cv d d v = n i v 5 6 4 . 3 =0 5 1a n i _ b f n , 1 k l c n , 0 k l c nv d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i n i _ b f , 1 k l c , 0 k l cv d d v , v 5 6 4 . 3 = n i v 0 =5 -a n i _ b f n , 1 k l c n , 0 k l c nv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 5 . 0v d d 5 8 . 0 -v v s i x k l c n , x k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n d d . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8624byi www.idt.com rev. c july 30, 2010 5 ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer t able 6a. ac c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c t able 4d. hstl dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 0 . 14 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 04 . 0v v x o 2 e t o n ; e g a t l o v r e v o s s o r c t u p t u o 0 40 6% v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 01 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n . d n u o r g o t . n o i t i d n o c n e v i g a t a g n i w s e g a t l o v t u p t u o o t t c e p s e r h t i w d e n i f e d : 2 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 3 6z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p? z h m 0 3 64 . 39 . 35 . 4s n ) ? ( t5 , 2 e t o n ; t e s f f o e s a h p c i t a t sv 3 . 3 = l e s _ l l p5 9 -0 35 5 1s p t ) o ( k s5 , 3 e t o n ; w e k s t u p t u o 0 5s p t ) c c ( t i j6 , 5 e t o n ; r e t t i j e l c y c - o t - e l c y c 5 3s p t ) ? ( t i j6 , 5 , 4 e t o n ; r e t t i j e s a h p 0 5 s p t l e m i t k c o l l l p 1s m t r e m i t e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 7s p t f e m i t l l a f t u p t u o% 0 8 o t % 0 20 0 30 0 7s p t w p h t d i w e s l u p t u p t u o 5 8 - 2 / d o i r e p t2 / d o i r e p t5 8 + 2 / d o i r e p ts p t a d e r u s a e m s r e t e m a r a p l l af x a m . e s i w r e h t o d e t o n s s e l n u . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n l a n g i s t u p n i k c a b d e e f d e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 2 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w , s n o i t i d n o c l l a s s o r c a : 3 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o t a d e r u s a e m . d e s u e c r u o s t u p n i e h t n o t n e d n e p e d s i r e t t i j e s a h p : 4 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 5 e t o n . z h m 2 2 6 f o y c n e u q e r f o c v t a d e z i r e t c a r a h c : 6 e t o n t able 5. i nput f requency c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i y c n e u q e r f t u p n i , 0 k l c n , 0 k l c 1 k l c n , 1 k l c 1 = l e s _ l l p5 2 . 1 30 3 6z h m 0 = l e s _ l l p0 3 6z h m t able 6b. ac c haracteristics , v dd = v dda = 3.3v10%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u t ) c c ( t i j1 e t o n ; r e t t i j e l c y c - o t - e l c y c 0 4s p . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 1 e t o n
ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer 8624byi www.idt.com rev. c july 30, 2010 6 p arameter m easurement i nformation c ycle - to -c ycle j itter p hase j itter and s tatic p hase o ffset o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v od t sk(o) nqx nq nqy qy d ifferential i nput l evel o utput s kew 3.3v c ore /1.8v o utput l oad ac t est c ircuit scope hstl qx nqx v cmr cross points v pp gnd clk0, clk1 nclk0, nclk1 v dd nqx qx nclk0, nclk1 clk0, clk1 nq0:nq4 q0:q4 t pd v dd , v dda gnd = 0v 3.3v5% or 10% v ddo 1.8v0.2v o utput p ulse w idth /p eriod pulse width t period v ddo 2 v ddo 2 v ddo 2 nq0:nq4 q0:q4 p ropagation d elay ? ? ? ? t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 (where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges) t (?) mean = static phase offset ? ? t (?) v oh v ol v oh v ol nclk0, nclk1 nfb_in fb_in t jit(?) = t (?) ? t (?) mean = phase jitter clk0, clk1
8624byi www.idt.com rev. c july 30, 2010 7 ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer a pplication i nformation figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2. s ingle e nded s ignal d riving d ifferential i nput as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics8624i provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v dda pin. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clkx nclkx vdd
ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer 8624byi www.idt.com rev. c july 30, 2010 8 f igure 3a. ics8624i hstl z ero d elay b uffer s chematic e xample c11 0.01u (u1-16) clk_sel (u1-17) zo = 50 ohm sel1 (u1-32) r4a 50 div_sel[1:0] = 01 vdd c4 0.1uf zo = 50 ohm r9 50 vdd=3.3v clk_sel r4b 50 c2 0.1uf ru5 sp vddo=1.8v sel1 c7 0.1uf vdda r2a 50 c1 0.1uf ru3 1k (u1-25) (155.5 mhz) vdd r10 50 zo = 50 ohm rd2 1k r7 10 c16 10u sp = space (i.e. not intstalled) r2b 50 zo = 50 ohm bypass capacitor located near the power pins vddo pll_sel rd4 sp 155.5 mhz sel0 c6 0.1uf pll_sel 3.3v ru4 1k vdd lvhstl_input + - vdd r8 50 (u1-24) sel0 rd5 1k u1 8624 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 sel0 sel1 clk0 nclk0 clk1 nclk2 clk_sel mr vdd nfb_in fb_in gnd gnd nq0 q0 vddo vddo nq1 q1 nq2 q2 nq3 q3 vddo vdd pll_sel vdda gnd gnd q4 nq4 vddo vddo ru2 sp rd3 sp (u1-9) 3.3v pecl driver c5 0.1uf l ayout g uideline the schematic of the ics8624i layout example is shown in figure 3a. the ics8624i recommended pcb board layout for this example is shown in figure 3b. this layout example is used as a general guideline. the layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the p.c. board. i nputs : clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : hstl o utput all unused hstl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
8624byi www.idt.com rev. c july 30, 2010 9 ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer f igure 3b. pcb b oard l ayout f or ics8624i the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors c1, c6, c2, c4, and c5, as close as possible to the power pins. if space allows, placement of the decoupling capacitor on the component side is preferred. this can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. maximize the power and ground pad sizes and number of vias capacitors. this can reduce the inductance between the power and ground planes and the component power and ground pins. the rc filter consisting of r7, c11, and c16 should be placed as close to the v dda pin as possible. c lock t races and t ermination poor signal integrity can degrade the system performance or cause system failure. in synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the shape of the trace and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ? the differential 50 output traces should have same length. ? avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. ? keep the clock traces on the same layer. whenever pos- sible, avoid placing vias on the clock traces. placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. ? make sure no other signal traces are routed between the clock trace pair. ? the matching termination resistors should be located as close to the receiver input pins as possible. gnd c1 pin 1 50 ohm traces c11 u1 vdd c7 c4 c5 vddo vdda c2 via r7 c16 c6
ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer 8624byi www.idt.com rev. c july 30, 2010 10 p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics8624i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8624i is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 3.465v * 135ma = 467.8mw ? power (outputs) max = 32.8mw/loaded output pair if all outputs are loaded, the total power is 5 * 32.8mw = 164mw total power _max (3.465v, with all outputs switching) = 467.8mw + 164mw = 631.8mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for the devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.632w * 42.1c/w = 111.6c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67. 8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47. 9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 7. t hermal r esistance ja for 32- pin lqfp, f orced c onvection
8624byi www.idt.com rev. c july 30, 2010 11 ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. hstl output driver circuit and termination are shown in figure 4. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load. pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = (v oh_min /r l ) * (v ddo_max - v oh_min ) pd_l = (v ol_max /r l ) * (v ddo_max - v ol_max ) pd_h = (1v/50 ) * (2v - 1v) = 20mw pd_l = (0.4v/50 ) * (2v - 0.4v) = 12.8mw total power dissipation per output pair = pd_h + pd_l = 32.8mw f igure 4. hstl d river c ircuit and t ermination v ddo v out rl 50 q1
ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer 8624byi www.idt.com rev. c july 30, 2010 12 r eliability i nformation t ransistor c ount the transistor count for ics8624i is: 1565 t able 8. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67. 8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47. 9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8624byi www.idt.com rev. c july 30, 2010 13 ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer p ackage o utline - y s uffix for 32 l ead lqfp n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 6 . 1 1 a 5 0 . 05 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 00 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 7 c c c 0 1 . 0 t able 9. p ackage d imenisions reference document: jedec publication 95, ms-026
ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer 8624byi www.idt.com rev. c july 30, 2010 14 t able 10. o rdering i nformation while the information presented herein has been checked for both accur acy and reliability, integrated device technology, inc. ( idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are impl ied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other extraordinary environmental requirement s are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use i n life support devices or critical medical instruments r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i y b 4 2 6 8i y b 4 2 6 8 s c ip f q l d a e l 2 3y a r tc 5 8 o t c 0 4 - t i y b 4 2 6 8i y b 4 2 6 8 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l i y b 4 2 6 8f l i y b 4 2 6 8 s c ip f q l " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l i y b 4 2 6 8f l i y b 4 2 6 8 s c ip f q l " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
8624byi www.idt.com rev. c july 30, 2010 15 ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a2 1 - 1 1. b 3 & a 3 s e r u g i f d e s i v e r 2 0 / 3 1 / 8 a 1 t a 3 t a 4 t 2 3 4 3 1 v d e s i v e r - e l b a t n o i t p i r c s e d n i p d d o t n o i t p i r c s e d s n i p y l p p u s e r o c m o r f . s n i p y l p p u s e v i t i s o p d a e r o t e t o n d e t c e r r o c - e l b a t n o i t c n u f t u p n i l o r t n o c z h m 0 3 6 o t z h m 0 5 2 . . . m o r f . z h m 0 0 7 o t 0 5 2 . . . v d e s i v e r - e l b a t y l p p u s r e w o p d d d a e r o t n o i t p i r c s e d r e t e m a r a p e g a t l o v y l p p u s e r o c m o r f . e g a t l o v y l p p u s e v i t i s o p v d e c a l p e r . n o i t a u q e n o i t a p i s s i d r e w o p d e t c e r r o c n i m _ h o v h t i w x a m _ h o . 2 0 / 8 / 0 1 b 2 t d 4 t b 6 t 3 4 5 5 c d e g n a h c - e l b a t s c i t s i r e t c a r a h c n i p n i . l a c i p y t f p 4 o t . x a m f p 4 . g n i t a r t u p t u o d e t a d p u - s g n i t a r m u m i x a m e t u l o s b a v d e g n a h c - e l b a t s c i t s i r e t c a r a h c c d l t s h x o d n a . x a m % 0 6 - . n i m % 0 4 o t . e t o n d e d d a v h t i w e l b a t s c i t s i r e t c a r a h c c a b 6 e l b a t d e d d a d d v = a d d . % 0 1 v 3 . 3 = . t e e h s a t a d e h t t u o h g u o r h t l t s h o t l t s h v l d e g n a h c 4 0 / 9 1 / 2 b 0 1 t 1 8 1 1 - 0 1 4 1 . t e l l u b e e r f - d a e l d e d d a d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r . n o i t a l u c l a c n o i t a p i s s i d r e w o p , s n o i t a r e d i s n o c r e w o p d e t c e r r o c . e t o n d n a r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 5 1 / 1 1 c0 1 t4 1 6 1 . s c i m o r f t d i h t i w r e t o o f / r e d a e h s ' t e e h s a t a d d e t a d p u . n m u l o c r e b m u n r e d r o / t r a p m o r f x i f e r p s c i d e v o m e r . e g a p t c a t n o c d e d d a 0 1 / 0 3 / 7
ics8624i l ow s kew , 1- to -5 d ifferential - to -hstl z ero d elay b uffer 8624byi www.idt.com rev. c july 30, 2010 16 we?ve got your timing solution. sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 tech support netcom@idt.com 6024 silver creek valley road san jose, ca 95138 ? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or m ay be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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